The proliferation of MIPS-based System-on-Chips (SoCs) in routers, gateways, and IoT devices has created a demand for debugging tools that are both accessible and hardware-agnostic. While standard JTAG (IEEE 1149.1) was designed for board-level testing, the MIPS-specific extension, EJTAG, introduces powerful CPU-halting and debugging capabilities.
Commercial solutions often require full JTAG probes (e.g., Ulx2, MIPS Navigator) costing thousands of dollars. ejtag tiny tools (often distributed as a suite of command-line executables) provides a "bare metal" interface to the EJTAG block. It allows developers to halt the CPU, read/write memory, and flash firmware using a simple Parallel Port (LPT) or USB-to-Parallel adapter. It represents a bridge between high-level software debugging and hardware-level interdiction.
A script or binary that uses EJTAG primitives to erase, program, and verify NOR or NAND flash memory—critical when the bootloader is dead. ejtag tiny tools software
Upon connection, the software executes the following sequence:
This method allows the software to achieve relatively high speeds compared to standard JTAG, as the on-CPU handler handles block memory transfers, reducing the overhead of the JTAG state machine transitions for every single word. This method allows the software to achieve relatively
ejtag-tiny bp set 0xbfc00000
The software intelligently manages scan chains, automatically detecting the number of TAPs (Test Access Ports) in your device. With adaptive clocking, it can push JTAG frequencies up to 50 MHz (depending on the probe hardware), ensuring fast firmware downloads and real-time variable watching. the MIPS-specific extension
One standout feature of EJTag Tiny Tools is "non-stop" mode. Traditional JTAG software halts the entire CPU when a breakpoint hits. The Tiny Tools software allows specific threads to stop while others continue to run, which is critical for RTOS (Real-Time Operating System) debugging.
