The full 1331-pin array is roughly a 33×31 grid with missing pins in the center and corners for mechanical keying.
| Pin Group | Pin Range / Zone | Description | |-----------|------------------|--------------| | VDD (Core) | Center + inner rings | CPU core voltage (SVI2 power stages) | | VDD_SOC | Outer sections near edges | SoC/I/O voltage (memory controller, PCIe, IF) | | VDD_CRYPTO | Dedicated region | Cryptographic co-processor power | | VDD_MISC | Scattered periphery | Minor logic and PLLs | | GND | Alternating pattern around power pins | Return current & noise isolation | | CLK (CPU) | F16, G16, H15, H16 | 100 MHz differential reference clock | | CLK (FCH/ICH) | C14, D15 | 25 MHz reference for chipset | | Reset (PROCHOT) | B11 | Thermal trip & reset signalling | | SVI2 (Power management) | A12–B14 | Serial VID interface 2.0 (voltage regulation control) | | PCIe lanes x16/x8/x4 | Multiple zones | Uplink to chipset & direct GPU slots | | DRAM channels (CH A/B) | B19–C25, etc. | Memory bus (288 pins total, shared with DDR4 interface) | | USB 2.0 / 3.0 | Edge pins | Direct from SoC (not through chipset) | | SATA | Edge pins | SoC direct SATA (usually ports 0–1) | | FCH (chipset) link | Dedicated bank | PCIe 3.0 x4 to Promontory chipset | am4 pin layout
⚠️ No official full 1331-pin grid is public — AMD keeps the exact layout under NDA. Third-party sources (like community socket diagrams) exist but are not guaranteed for OEM validation. The full 1331-pin array is roughly a 33×31
Before dissecting the layout, one must understand the physical connector type. Unlike Intel’s LGA (Land Grid Array), AMD’s AM4 uses PGA (Pin Grid Array). ⚠️ No official full 1331-pin grid is public